This application relates generally to processing systems, and, more particularly, to prefetching instructions using predicted branch target addresses in processing systems.
Processing systems typically implement a hierarchical cache complex, e.g., a cache complex that includes an L2 cache and one or more L1 caches. For example, in a processing system that implements multiple processor cores, each processor core may have an associated L1 instruction (L1-I) cache and an L1 data (L1-D) cache. The L1-I and L1-D caches may be associated with a higher level L2 cache. When an instruction is scheduled for processing by the processor core, the processor core first attempts to fetch the instruction for execution from the L1-I cache, which returns the requested instruction if the instruction is resident in a cache line of the L1-I cache. However, if the request misses in the L1-I cache, the request is forwarded to the L2 cache. If the request hits in the L2 cache, the L2 cache returns the requested line to the L1-I cache. Otherwise, the L2 cache may request the line from a higher-level cache or main memory.
Prefetching may be used to populate the lines of the L1-I cache when the prefetcher can identify patterns (e.g., requests for a sequence of addresses) that can be used to predict the addresses of subsequent requests. For example, the prefetcher can use sequential addresses of two misses to the L1-I cache to predict that the L1-I cache is likely to receive requests for additional addresses that follow from the missed addresses in the same sequence. The prefetcher may therefore prefetch one or more addresses along the sequence into the L1-I cache so that these cache lines are available when requested.